no code implementations • 23 Jun 2021 • Shubham Negi, Indranil Chakraborty, Aayush Ankit, Kaushik Roy
The hardware efficiency (energy, latency and area) as well as application accuracy (considering device and circuit non-idealities) of DNNs mapped to such hardware are co-dependent on network parameters, such as kernel size, depth etc.
no code implementations • 15 Mar 2020 • Indranil Chakraborty, Mustafa Fayez Ali, Dong Eun Kim, Aayush Ankit, Kaushik Roy
Further, using the functional simulator and GENIEx, we demonstrate that an analytical model can overestimate the degradation in classification accuracy by $\ge 10\%$ on CIFAR-100 and $3. 7\%$ on ImageNet datasets compared to GENIEx.
Emerging Technologies
1 code implementation • 23 Jan 2020 • Gobinda Saha, Isha Garg, Aayush Ankit, Kaushik Roy
A minimal number of extra dimensions required to explain the current task are added to the Core space and the remaining Residual is freed up for learning the next task.
no code implementations • 11 Jun 2019 • Maryam Parsa, Aayush Ankit, Amirkoushyar Ziabari, Kaushik Roy
The ever increasing computational cost of Deep Neural Networks (DNN) and the demand for energy efficient hardware for DNN acceleration has made accuracy and hardware cost co-optimization for DNNs tremendously important, especially for edge devices.
1 code implementation • 4 Jun 2019 • Indranil Chakraborty, Deboleena Roy, Isha Garg, Aayush Ankit, Kaushik Roy
The `Internet of Things' has brought increased demand for AI-based edge computing in applications ranging from healthcare monitoring systems to autonomous vehicles.
no code implementations • 1 Feb 2019 • Indranil Chakraborty, Deboleena Roy, Aayush Ankit, Kaushik Roy
In this work, we propose extremely quantized hybrid network architectures with both binary and full-precision sections to emulate the classification performance of full-precision networks while ensuring significant energy efficiency and memory compression.
no code implementations • 29 Jan 2019 • Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-mei Hwu, John Paul Strachan, Kaushik Roy, Dejan S Milojicic
We also present the PUMA compiler which translates high-level code to PUMA ISA.
Emerging Technologies Hardware Architecture
no code implementations • 1 Jul 2018 • Amogh Agrawal, Akhilesh Jaiswal, Deboleena Roy, Bing Han, Gopalakrishnan Srinivasan, Aayush Ankit, Kaushik Roy
In this paper, we demonstrate how deep binary networks can be accelerated in modified von-Neumann machines by enabling binary convolutions within the SRAM array.
Emerging Technologies
no code implementations • 7 Dec 2017 • Syed Shakib Sarwar, Aayush Ankit, Kaushik Roy
We propose an efficient training methodology and incrementally growing DCNN to learn new tasks while sharing part of the base network.
no code implementations • 26 Aug 2017 • Aayush Ankit, Abhronil Sengupta, Kaushik Roy
Implementation of Neuromorphic Systems using post Complementary Metal-Oxide-Semiconductor (CMOS) technology based Memristive Crossbar Array (MCA) has emerged as a promising solution to enable low-power acceleration of neural networks.
no code implementations • 20 Feb 2017 • Aayush Ankit, Abhronil Sengupta, Priyadarshini Panda, Kaushik Roy
In this paper, we propose RESPARC - a reconfigurable and energy efficient architecture built-on Memristive Crossbar Arrays (MCA) for deep Spiking Neural Networks (SNNs).
no code implementations • 12 Sep 2016 • Priyadarshini Panda, Aayush Ankit, Parami Wijesinghe, Kaushik Roy
We evaluate our approach for a 12-object classification task on the Caltech101 dataset and 10-object task on CIFAR-10 dataset by constructing FALCON models on the NeuE platform in 45nm technology.