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Neural Network Training on In-memory-computing Hardware with Radix-4 Gradients
Deep learning training involves a large number of operations, which are dominated by high dimensionality Matrix-Vector Multiplies (MVMs).
A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computing
Chip measurements show an energy efficiency of 152/297 1b-TOPS/W and throughput of 4. 7/1. 9 1b-TOPS (scaling linearly with the matrix/input-vector element precisions) at VDD of 1. 2/0. 85V.
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