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Found 12 papers, 1 papers with code
A Calibratable Model for Fast Energy Estimation of MVM Operations on RRAM Crossbars
The surge in AI usage demands innovative power reduction strategies.
CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures
The demand for efficient machine learning (ML) accelerators is growing rapidly, driving the development of novel computing concepts such as resistive random access memory (RRAM)-based tiled computing-in-memory (CIM) architectures.
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications
The ion-sensitive field-effect transistor (ISFET) is an emerging technology that has received much attention in numerous research areas, including biochemistry, medicine, and security applications.
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks
Hereby, the presented work offers a starting point for the design and evaluation of future-generation logic locking in the era of machine learning.
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities
In the past decade, a lot of progress has been made in the design and evaluation of logic locking; a premier technique to safeguard the integrity of integrated circuits throughout the electronics supply chain.
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework
With the growing demands of consumer electronic products, the computational requirements are increasing exponentially.
Hardware Architecture
An Investigation on Inherent Robustness of Posit Data Representation
Moreover, in 100% of the tested machine-learning applications, the accuracy of posit-implemented systems is higher than the classical floating-point-based ones.
Hardware Architecture
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach
The first approach is based on a simple feedforward fully connected neural network.
Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect
Our mapping strategy and system setup is scaled starting from the single core level up to 128 cores, thereby showing the limits of the selected approach.
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism
To the best of our knowledge, this is the first-ever integration of quire with a RISC-V core.
Hardware Architecture
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration
In recent years, neural networks have surpassed classical algorithms in areas such as object recognition, e. g. in the well-known ImageNet challenge.
EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment
Furthermore, EURETILE investigates and implements the innovations for equipping the elementary HW tile with high-bandwidth, low-latency brain-like inter-tile communication emulating 3 levels of connection hierarchy, namely neural columns, cortical areas and cortex, and develops a dedicated cortical simulation benchmark: DPSNN-STDP (Distributed Polychronous Spiking Neural Net with synaptic Spiking Time Dependent Plasticity).
