2 code implementations • 16 Apr 2018 • Javier Duarte, Song Han, Philip Harris, Sergo Jindariani, Edward Kreinar, Benjamin Kreis, Jennifer Ngadiuba, Maurizio Pierini, Ryan Rivera, Nhan Tran, Zhenbin Wu
For our example jet substructure model, we fit well within the available resources of modern FPGAs with a latency on the scale of 100 ns.