1 code implementation • 9 Apr 2024 • Afzal Ahmad, Linfeng Du, Zhiyao Xie, Wei zhang
We present a technique that allows searching for training proxies that reduce the cost of benchmark construction by significant margins, making it possible to construct realistic NAS benchmarks for large-scale datasets.
1 code implementation • 14 Dec 2023 • Qijun Zhang, Shiyu Li, Guanglei Zhou, Jingyu Pan, Chen-Chia Chang, Yiran Chen, Zhiyao Xie
Based on the formulation, we propose PANDA, an innovative architecture-level solution that combines the advantages of analytical and ML power models.
no code implementations • 4 Dec 2023 • Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Yiran Chen
The application of Machine Learning (ML) in Electronic Design Automation (EDA) for Very Large-Scale Integration (VLSI) design has garnered significant research attention.
1 code implementation • 10 Aug 2023 • Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie
In this work, we propose an open-source benchmark named RTLLM, for generating design RTL with natural language instructions.
no code implementations • 7 Jun 2022 • Zhiyao Xie
In this dissertation, I present multiple fast yet accurate ML models covering a wide range of chip design stages from the register-transfer level (RTL) to sign-off, solving primary chip-design problems about power, timing, interconnect, IR drop, routability, and design flow tuning.
no code implementations • 30 Mar 2022 • Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen
To further strengthen the results, we co-design a customized ML model FLNet and its personalization under the decentralized training scenario.
no code implementations • 20 Mar 2022 • Zhiyao Xie, Jingyu Pan, Chen-Chia Chang, Yiran Chen
The growing IC complexity has led to a compelling need for design efficiency improvement through new electronic design automation (EDA) methodologies.
no code implementations • 3 Dec 2020 • Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chun-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen
The rise of machine learning technology inspires a boom of its applications in electronic design automation (EDA) and helps improve the degree of automation in chip designs.
no code implementations • 27 Nov 2020 • Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen
Net length is a key proxy metric for optimizing timing and power across various stages of a standard digital design flow.
no code implementations • 26 Nov 2020 • Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen
IR drop constraint is a fundamental requirement enforced in almost all chip designs.
no code implementations • 26 Nov 2020 • Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
Experimental results on benchmark circuits show that our approach achieves 25% improvement in design quality or 37% reduction in sampling cost compared to random forest method, which is the kernel of a highly cited previous work.
no code implementations • 26 Nov 2020 • Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen
Moreover, the proposed CNN model is general and transferable to different designs.