no code implementations • 16 Apr 2024 • Adarsha Balaji, Ramyad Hadidi, Gregory Kollmer, Mohammed E. Fouda, Prasanna Balaprakash
Our NAS and HPS of (1) BraggNN achieves a 31. 03\% improvement in bragg peak detection accuracy with a 87. 57\% reduction in model size, and (2) PtychoNN achieves a 16. 77\% improvement in model accuracy and a 12. 82\% reduction in model size when compared to the baseline PtychoNN model.
no code implementations • 10 Mar 2022 • Shihao Song, Adarsha Balaji, Anup Das, Nagarajan Kandasamy
First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS.
no code implementations • 17 Feb 2022 • Phu Khanh Huynh, M. Lakshmi Varshika, Ankita Paul, Murat Isik, Adarsha Balaji, Anup Das
Here, we provide a comprehensive overview of such frameworks proposed for both, platform-based design and hardware-software co-design.
no code implementations • 23 Nov 2021 • M. Lakshmi Varshika, Adarsha Balaji, Federico Corradi, Anup Das, Jan Stuijt, Francky Catthoor
We propose a system software framework called SentryOS to map SDCNN inference applications to the proposed design.
no code implementations • 4 Aug 2021 • Shihao Song, Harry Chong, Adarsha Balaji, Anup Das, James Shackleford, Nagarajan Kandasamy
We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware.
no code implementations • 5 May 2021 • Shihao Song, Jui Hanamshet, Adarsha Balaji, Anup Das, Jeffrey L. Krichmar, Nikil D. Dutt, Nagarajan Kandasamy, Francky Catthoor
We propose a new architectural technique to mitigate the aging-related reliability problems in neuromorphic systems, by designing an intelligent run-time manager (NCRTM), which dynamically destresses neuron and synapse circuits in response to the short-term aging in their CMOS transistors during the execution of machine learning workloads, with the objective of meeting a reliability target.
no code implementations • 4 May 2021 • Adarsha Balaji, Shihao Song, Twisha Titirsha, Anup Das, Jeffrey Krichmar, Nikil Dutt, James Shackleford, Nagarajan Kandasamy, Francky Catthoor
Recently, both industry and academia have proposed many different neuromorphic architectures to execute applications that are designed with Spiking Neural Network (SNN).
no code implementations • 22 Mar 2021 • Twisha Titirsha, Shihao Song, Adarsha Balaji, Anup Das
Based on such formulation, we first evaluate the role of a system software in managing the energy consumption of neuromorphic systems.
no code implementations • 27 Nov 2020 • Adarsha Balaji, Anup Das
Spiking Neural Networks (SNNs) are efficient computation models to perform spatio-temporal pattern recognition on {resource}- and {power}-constrained platforms.
no code implementations • 19 Sep 2020 • Adarsha Balaji, Shihao Song, Anup Das, Jeffrey Krichmar, Nikil Dutt, James Shackleford, Nagarajan Kandasamy, Francky Catthoor
With growing model complexity, mapping Spiking Neural Network (SNN)-based applications to tile-based neuromorphic hardware is becoming increasingly challenging.
no code implementations • 11 Jun 2020 • Adarsha Balaji, Thibaut Marty, Anup Das, Francky Catthoor
In this paper, we propose a design methodology to partition and map the neurons and synapses of online learning SNN-based applications to neuromorphic architectures at {run-time}.
1 code implementation • 7 Apr 2020 • Shihao Song, Adarsha Balaji, Anup Das, Nagarajan Kandasamy, James Shackleford
First, we propose a greedy technique to partition an SNN into clusters of neurons and synapses such that each cluster can fit on to the resources of a crossbar.
1 code implementation • 21 Mar 2020 • Adarsha Balaji, Prathyusha Adiraju, Hirak J. Kashyap, Anup Das, Jeffrey L. Krichmar, Nikil D. Dutt, Francky Catthoor
We also use PyCARL to analyze these SNNs for a state-of-the-art neuromorphic hardware and demonstrate a significant performance deviation from software-only simulations.
no code implementations • 1 Nov 2019 • Adarsha Balaji, Shihao Song, Anup Das, Nikil Dutt, Jeff Krichmar, Nagarajan Kandasamy, Francky Catthoor
Our framework first extracts the precise times at which a charge pump in the hardware is activated to support neural computations within a workload.
no code implementations • 4 Sep 2019 • Adarsha Balaji, Anup Das, Yuefeng Wu, Khanh Huynh, Francesco Dell'Anna, Giacomo Indiveri, Jeffrey L. Krichmar, Nikil Dutt, Siebren Schaafsma, Francky Catthoor
SpiNePlacer then finds the best placement of local and global synapses on the hardware using a meta-heuristic-based approach to minimize energy consumption and spike latency.